DMDs are a type of spatial light modulator, characterized by array of micro-mechanical pixel elements having reflective surfaces. The pixel elements are electronically addressable, such that each can be selectively positioned to direct light in either an "on" or "off" position. An addressed array of pixel elements represents an image frame, with the image being formed as a result of which pixel elements direct light to an image plane. The image can be captured by means of opto-electrical devices and used to generate a display or printed copy.
Typically, the pixel elements of a DMD have associated memory cells for storing the binary signal that will drive the pixel element to its on or off position. An advantage of many DMD designs is that the pixel array, as well as the memory cells and addressing circuits can be fabricated with integrated circuit techniques.
In general, DMD pixel architectures may be distinguished by type of deformation modes, namely torsion beam or cantilever beam. Torsion beam pixels consist of a thick reflective beam suspended over an air gap and connected between two supports by two thin torsion hinges that are under tension. When an address electrode, underlying one half of the torsion beam, is energized, the torsion hinges are twisted and the beam rotates about the axis of the hinges. Cantilever beam pixels consist of a thick reflective beam suspended over an air gap, connected by a thin cantilever hinge to a support. When an underlying address electrode is energized, the cantilever hinge bends and the beam tip is deflected toward the address electrode.
Fabrication of both torsion beam and cantilever beam pixels is typically on top of an address circuit already fabricated on a semiconductor wafer. Once the address circuit is formed, a planarizing spacer layer is placed on the wafer. This spacer layer provides a smooth surface on which to form the hinges and beams. A metal layer is then patterned in the desired shape of the hinges and beams. Finally, the spacer layer is removed from under the beams by an isotropic plasma etch to form the air gap between the beams and address electrodes.
In many fabrication processes, it is desirable to perform the metal patterning at the wafer level. Then, a protective coating is placed over the entire wafer, the wafer is sawed into chips, and the protective coating is removed. Then, the plasma etch is performed to remove the spacer, such that undercutting of the metal pattern occurs to form air gaps. Thus, the spacer removal is at the chip level.
A problem with existing fabrication processes is that the patterning of the metal layer results in a contaminating layer on top of the spacer. This contaminating layer is a mixture of materials that is not easily etched.
FIG. 1 illustrates a chip 10 having this contaminating layer 11 over the spacer layer 12. Chip 10 is one of many chips whose various layers have been fabricated in wafer form, with the wafer then being sawed into the chips. Before sawing, a protective coating 18 was deposited over the entire wafer. FIG. 1 also shows the address circuitry 13, mirror beam 14, hinge 15, support post 16 formed in prior fabrication steps, as well as an oxide layer 17 used for metal patterning, which has not yet been removed. When the time comes for removal of the spacer layer 12, the contaminating layer 11 interferes with this removal. Incomplete removal results in "webbing" between the mirror beams 14 and limits their performance.
Previous efforts to remove the contaminating layer 11 have been performed "as needed". Thus, because spacer layer 12 is not removed until after the wafer is cut into chips, removal of the contaminating layer 11 is also performed at the chip level. However, this is unnecessarily time consuming. A need exists for a fabrication method that avoids the need for a chip level cleanup of contaminants left by metal patterning.